In chronological order (oldest first)

1.  In the early 1970s, when few knew what a computer was, and pioneers were creating the available and cost effective technology:  Board level CPU for Astronautics Corporation in Milwaukee.  Took existing 8 bit TTL design using hardware TCU supporting only programmed I/O, revised into completely new TTL & NMOS design using horizontally microprogrammed TCU with 8 and 16 bit capability with internal and external DMA and interrupt driven I/O.  Also took eight line text CRT interface, revised into 40 line text and graphics design.  Architecture of first successful word processor for the military named Standard Remote Terminal for Autodyn network, first affordable computer with microcoded TCU variable instruction set and computer controlled I/O.

2.  Board level CPU for Cutler Hammer in Milwaukee.  Aided in the design of an 8 bit CMOS A series central processor.  Originated design option based on microprogrammed TCU.  First processor to control a real time fault tolerant networking system, in this case purpose built for automation of individual CNC machinery in a large factory setting through a central commercial minicomputer computer for all individual machine sensors and actuators.  First successful factory automation technology.  First successful dynamically reconfigurable networking product.  Also designed trouble shooting service subcomputer used to identify com link problem and location, gather performance parameters, and manage real time reconfiguration - no data loss.

3.  Board level "math coprocessor" for commercial Data General Eclipse minicomputer for GE Xray in Milwaukee.  Took existing Xray tomography product that required overnight computing, because of software algorithm higher mathematics execution, and created first real time reduction of floating point array data {convolution} execution.  First successful Xray tomography technology upgrade to real time performance, first example of "co-processor" commercial computer architecture.

4.  Board level word processor for IBM Office products Division in Austin.  Company had Office System 6, desired a real "sit on the desk" product similar to Astronautics SRT.  Contributed to design of first successful IBM word processor product (Displaywriter).

5.  IBM's and my first chip level CPUs in Austin.  Reviewed Motorola 68000 architecture and worked with that company to provide a dual level microprogrammed TCU to implement IBM 360 instruction set in the 68000 chip.  Promoted to architecture group in IBM.  Contributed to Research Office Products Miniprocessor {ROMP} VLSI architecture and systems design.  Design implemented to silicon by University of Texas in Austin.  First example of modern "supercomputer" CPU.

6.  Data Point's first chip level CPU in Austin/San Antonio.  "Redwood" project VLSI architecture.  Job description was to combine the instruction sets of many different and varied board level existing CPU designs into a single VLSI CPU that would execute all existing company networking software without modification.  This company was the first successful commercial networking product producer {ArcNet}.  This effort is the first known user loadable microcoded VLSI architecture.

X.  A slight interruption occurred for a Master's Degree at the University of Texas in Austin, in two semesters.

7.  Joined Mostek, a semiconductor company, in Carrollton Texas as design engineer.  Became Manager Advanced Development.  Led 68200 VLSI microcomputer design group.  Formed and led the group in the definition, systems design, and architecture of the first CPU designed specifically to efficiently support a structured high level language {Pascal}.  Later second sourced by Motorola as part of its "family".

8.  Ether net VLSI for Mostek in Carrollton.  Significant contribution to team already formed to design the first networking VLSI.  Contribution included partitioning, system design, internal CPU definition, instruction set determination, and design contribution.

X.  A slight interruption occurred to become faculty at the University of Florida.  Created courses in logic design, computer architecture, advanced design of computer architectures, and helped create the modern standard "computer engineering" curriculum from EE and CS separate degree programs.

9.  Geometric Arithmatic Parallel Processor {GAPP}, a real time vision recognition, dynamically partitionable, dynamically fault reconfigurable, array processor (SIMD) for Martin Marietta in Orlando.  Each IC contained 72 microprocessors, composed of a single TCU and multiple ALU-register sets.  Array grows in X and Y dimensions to match a required image array of pixels matrix, and decimates in time to allow fault reconfiguration and price/performance options.  First successful SIMD VLSI.  First successful real time image recognition.  Responsibility included addition to instruction set {If then, case, etc based on if any, if all, if none}, redesign for performance enhancement, and design of fault reconfiguration switching at internal IC level and external array coordination.  Non-classified version is the 45CG72 from NCR.

10.  ARSA for Martin Marietta in Orlando.  First Associative Real Time System Architecture for artificial intelligence utilizing partitionable system design to allow for computing attribute mission dependent implementation.  Completely responsible for the entire architecture, much of which was personal design.

11.  SAM VLSI for AMD in Austin.  First "data structures on silicon" approach to solving the "Von Neuman bottleneck" problem of standard computer architecture performance.  A chip with a RAM memory array, partitionable inside the VLSI in word size at the expense of number of words capacity, which also contains a microprogrammable custom TCU state machine.  Supports the ability to increase system CPU performance by one to two orders of magnitude by eliminating all of the CPU "effective address" calculations required for a user program to access a data structure.  Personal responsibility included instruction set definition, microcoding of the TCU state machine, and chip to chip communications and synchronization network design.

12.  AM95C85 sort buffer chip for AMD in Austin.  An application specific subset of the above.

13.  A custom GPS satellite navigation system GaAs CPU.  Given that any problem can be solved in a general purpose CPU, real time performance of a convolution on a large array of data can be accomplished by an implementation in a ten times faster substrate utilizing a problem customized architecture to allow pipelining and parallel data structure descimation.

X.  A slight interruption occurred to become faculty at Texas A&M University in College Station.  Created courses in logic design, computer architecture, first course in Texas in CMOS design, first course anywhere in silicon synthesis.  Curriculum development committee.

14.  First aviation GPS receiver.

15.  First GPS-Loran aviation receiver.

16.  First aviation moving map, based on Loran-C navigation technology, improved to include precision navigation (localizer approach) and modified to GPS navigation technology.

17.  First Cat IIIc capable instrument landing system with point to point navigation capability for aircraft.

18.  First development of "all in the sky" satellite navigation solution algorithm, using every phase point transmitted for a twelve satellite GPS constellation.  {12x11x10x9x1000 convolutions per second, utilizing five chips to get there)

19.  System design of custom satellite navigation system CMOS CPU for Analog Devices Incorporated in Austin.  Essentially the above, in a degraded computationally intensive form for 5 convolutions per second utilizing the Glonass navigational satellite system.  Though not implemented, this design should improve on the above seven sigma 104' dispersion to three sigma 10' dispersion.  Considerably more affordable, in addition to more accurate, in an easily produced technology.

20.  First aviation transponder proximity detector, a collision avoidance system for general aviation (privately owned aircraft).

21.  First passive radar.

22.  First Air traffic Control replacement technology that forms all of the FAA objectives for future radar capability and also for aircraft autonomous collision avoidance (terrain, obstruction, other aircraft, runway incursion).