KEY WORDS:
System on a chip, SOC, ASIC, VLSI, FPGA, Verilog, logic, synthesis, layout, IC, design, silicon, test, debug, microcontroller, microcomputer, firmware, instruction set, DSP, digital, CMOS, pre-IPO

EXPERIENCE:
Architect, design and implement next-generation digital integrated circuit chips and systems-on-chip (SOC).  Contribute to all phases of ASIC design flow, including architectural decisions, logic design and synthesis, functional and pre- and post-layout timing verification, and initial post-silicon testing, successfully driving major chip modules through design, verification, test, and debug using disciplined design methodologies and the latest EDA tools.

QUALIFICATIONS:
· BS and MS in Electrical and Electronic and Computer Engineering with many years experience with ASIC & FPGA design
· Completed many chips successfully
· Verilog behavioral & RTL & structural modeling and testing, logic and system design
· Logic synthesis, timing analysis and verification and chip integration
· Knowledge of synchronous and asynchronous state machines and microcontroller  and microcomputer architectures
· DSP and non-VonNeuman architecture and implementation experience
· Drive to succeed with experience leading and accomplishing team challenges, interested in a pre-IPO startup

INTEREST:
New product systems design, Von Neuman and DSP CPU & custom design digital VLSI & SoC IC architecture & implementation, IP generation and implementation, FPGA design implementation.  Custom hardware design implementation utilizing Verilog for synthesis, test bench simulation and verification.  Use of EDA tools for post layout parameters extraction and verification (physically knowledgeable synthesis design tools flow).  Integrate hardware and software requirements into design solutions, design of FPGA and gate array and semicustom and full custom ASIC integrated circuit implementations to provide superior response time / computational power / throughput.  Experience with synthesis techniques, involving architectural enhancements for performance, specializing in complete solutions to tough problems.

TECHNICAL ABILITY:
Deliver Design, Design Optimization, Verification, Integration, and Analysis services to help IC development teams overcome critical design bottlenecks.  Contribute directly to IC design success by working as a member of development team, leveraging experience and design for synthesis tools best practices to have immediate impact on design projects while transferring valuable knowledge and methods for use on future projects.  Ability to work with a broad array of individuals in a cross-functional team.  Involvement in all aspects of IC development, including design specification, project planning, HDL code development, functional verification, structural implementation and optimization, physical design implementation, timing verification and closure both pre and post layout.  Responsibilities include assessing customer needs, IC design, design methodology development, and technical project leadership.  Both IC design experience, and a strong interest and contribution to leading-edge design and design tool issues, exceptional communication skills, and a customer service orientation.

New product systems design, specialized computer and CPU and IC hardware architecture, specifications development, Verilog RTL behavioral and structural design and certification, physically knowledgeable synthesis, vendor qualification, technical performance evaluation, standards compliance testing.  Design experience includes design of complete microprocessors (RISC & CISC & SIMD & MIMD & DSP), microprocessor based computer systems, digital communications systems, bus structure specification, peripheral interface design, digital state machine design, analog design, and RF design.  Specialization is custom chip architectures for high throughput on unique algorithm processing.  Familiar with bit slice design architecture, including instruction set definition and execution timing (timing and control unit firmware).  Implementation experience includes user programmable components from PLDs to FPGAs, semicustom gate array logic design and specification, CMOS custom integrated circuit partitioning & floor-planning, and physical synthesis for performance IC hardware design implementation.

Consulting experience includes prototype model assembly, troubleshooting, design verification, regulatory certification, manufacturing engineering, component qualification, failure analysis, schematic capture, printed circuit board layout, functional and timing simulation, bill of materials documentation, testing specifications and procedures, and laboratory analysis.

Experienced in writing, presentations, project organization, technical options evaluation, development group technical direction, product and hardware design implementation, research, development, and technology instruction.

WORK HISTORY (latest toward earlier):
EDA IC design tools development and validation testing for physical synthesis (a revolutionary new IC design methodology). Avionics design for navigation and collision avoidance (first avionics for GPS navigation, first moving map, first GPS with Loran-C augmentation, first GNSS instrument landing system, first GNSS collision avoidance/terrain avoidance/obstruction avoidance). One of two architects on unique high performance 3D graphics accelerator IC. Geophysical instrumentation design. Digital cable television equipment design. Architect and design implementation on first intelligent memory chip; a method to increase Von Neuman performance by one to three orders of magnitude with slight modifications to the operating system. Several military weapons guidance and secure communications systems. Development of an artificial intelligence correlation computer for real time visual and acoustic object recognition and identification. Architecture and implementation of GAPP; a SIMD DSP for object targeting for autonomous military weapons. Started as engineer and left as Manager of Advanced Development of a semiconductor company - 68200 first HLL uP, and first ether net chip. Returned to University of Texas for an MSEE in computer architecture, completed in two semesters. Brought to Texas by IBM to work on ROMP and Displaywriter, which led to the 286 IBM PC. Architecture and implementation of first fault tolerant distributed computer control network. Floating point accelerator architect and design implementation for first real time Xray tomography. CPU architect and design implementation of first word processor (for the military).  Development of digital electronics for the squad car.  Development of first nuclear ionization smoke detector.  Development of electric motor production technology and quality control instrumentation.

Engineering & product development applications have included technical strategic marketing, technical product planning, product design engineering, hardware and firmware design implementation, customer product introduction & support, consulting and contract engineering. Demonstrated growth from the levels of senior engineer (technical design), to staff engineer (technical design team leader), to technique development engineer (systems design and architecture management), to manager advanced development (entire development project responsibility for multiple IC developments), to member technical staff (advanced technology means and methods).  Require hands on engineering design.

Professor at University of Florida and Texas A&M University. Autonomous authority covering text selection, syllabus content, lecture delivery, projects content, exam production, and student grading in the subjects of (built a core of the following courses) logic design, microprocessor based hardware design, computer architecture, IC design, and logic synthesis.  Created from personal notes the first CMOS integrated circuit design course taught in the state of Texas.  Created from research the first silicon compiler design course taught.  Faculty of Embry Riddle Aeronautical University.  Mentor at University of Texas department of Aerospace Engineering, taking students through projects involving FAA certification of avionics.

EDUCATION:

Post Graduate Work, University of Florida, Tampa 4.0/4.0
Computer Architecture
#18 of top 25 U.S. engineering schools, U.S. News, 3-23-92, pp. 82

Post Graduate Work, University of Texas, Dallas 3.8/4.0
Management & Administrative Science
Completed approximately 1/2 of MBA degree program

Master of Science, University of Texas, Austin 3.5/4.0
Electronic and Computer Engineering
Normally a five semester curriculum, completed in two semesters
#8 of top 25 U.S. engineering schools

Bachelor of Science, University of Wisconsin, Madison 3.4/4.0
Electronics and Computer Engineering
Honors graduate, Dean's list, honors scholarship recipient
#12 of top 25 U.S. engineering schools

EQUIPMENT LIST:
Owned equipment & laboratory facilities

EXAMPLE CONTRIBUTIONS:
In most engineering careers, there is the opportunity to participate in only one part of only one new and unique microprocessor architecture and design implementation.  The following is a partial list in chronological order of those CPUs for which responsibility and authority were accepted and a working CPU produced.

As the smallest resolvable dimension in IC implementation decreases, it becomes impossible to determine if a rendered design will continue to work as the higher level Verilog simulated.  This published ISD magazine article explains why that is, and the only known means of solving that problem.  Contribution can be reviewed by clicking on Projects then OLA.  Participation can be gauged by going to the bottom of the first page and searching on "peshak".

We had the navigation problem.  Where are you (position), where are you going (velocity), needs to work anywhere on the planet to the degree that you can bet your life on being right.  Land an airplane in fog, avoid reefs with a ship, even find a street address for 911 emergency services.  Here is recognition for international contribution (in the left window, click on LINKS) in reducing the solution to inexpensive integrated circuits and commercial products.

We still presently have the worst airline delays ever experienced, coupled with the lowest levels of safety in the air (and under) ever experienced.  The problems of runway incursion, of collision avoidance, of controlled fight into terrain, and of striking obstructions such as towers during approach and takeoff.  From the library of congress, here is my, the only, solution to the entire problem set, then cost reduced by rendering into integrated circuits then completing productization for avionicsproducingcompanies.